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	Some universities give all their classes out to the public. Thank you so much.		Some universities give all their classes out to the public. Thank you so much.

	* [http://pages.hmc.edu/harris/cmosvlsi/4e/index.html Harvey Mudd] ~~(Excellent textbook and slides, but no lectures)~~		* [http://pages.hmc.edu/harris/cmosvlsi/4e/index.html Harvey Mudd]
			** The textbook is amazing and almost everyone uses it.
			** Lecture slides are good, but there is no video.

	* [http://cmosedu.com/jbaker/courses/courses.htm Las Vegas] ~~(Excellent professor and )~~		* [http://cmosedu.com/jbaker/courses/courses.htm Las Vegas]
	** There are almost 10 years of (video) lectures, homework assignments, and labs to be viewed here.		** There are almost 10 years of (video) lectures, homework assignments, and labs to be viewed here.
	** If you navigate his website, [http://www.cmosedu.com/jbaker/courses/ee421L/ a good resource] is under <code><year>/students/<student></code> since each student was required to make a website stepping through their work.		** If you navigate his website, [http://www.cmosedu.com/jbaker/courses/ee421L/ a good resource] is under <code><year>/students/<student></code> since each student was required to make a website stepping through their work.

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2022-02-21T04:53:19Z

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= Information on ASIC design =

ASIC design is interesting because it seems to not have caught up with Web3.0. There are maybe 2-3 YouTube videos that describe layout strategies, no one talks about ASIC design and anything else is on broken websites or theoretical academic papers with no practical, real-world use besides for companies who've already got a baseline down. Mostly, [https://shell.lug.mtu.edu/wiki/index.php?title=ASIC_Design#Layout_of_a_chip the layout procedure] seems to be heavily missing in tutorials. There will be an abundant amount of resources on layout so that one can glean as much information from it as possible. This is an attempt at making learning ASIC design a smooth process into advanced topics.

= Learning ASIC Design =

One should have a basic understanding of assembly and what each instruction does. A general idea, rather than intimate knowledge behind a CPU should be simple enough to find online.

== Universities ==

Some universities give all their classes out to the public. Thank you so much.

* [http://pages.hmc.edu/harris/cmosvlsi/4e/index.html Harvey Mudd] (Excellent textbook and slides, but no lectures)

* [http://cmosedu.com/jbaker/courses/courses.htm Las Vegas] (Excellent professor and )
** There are almost 10 years of (video) lectures, homework assignments, and labs to be viewed here.
** If you navigate his website, [http://www.cmosedu.com/jbaker/courses/ee421L/ a good resource] is under <code><year>/students/<student></code> since each student was required to make a website stepping through their work.
** [http://cmosedu.com/videos/cadence/cadence_videos.htm His cadence tutorials] are a godsend and MTU's labs only go to his <emph>first</emph> tutorial. There are five after that.

* [http://web.archive.org/web/20171005190751/https://www.ece.ncsu.edu/asic/2013/index.htm NCSU] (No longer public, but archive.org still has it)
** No longer public, but available of archive.org.
**

* [http://web.archive.org/web/20190207120325/http://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/F11.html UC Davis]
** No longer public, but available on archive.org.
** [http://web.archive.org/web/20190201021310/http://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/labs/ The labs] are of good quality.

== Digital logic ==

Digital logic is the basic building blocks of ASIC design. [https://lug.mtu.edu/minutes/spring2022/meeting03.html A LUG lecture] on this topic discussed the basics of digital logic, though it is recommended to follow the [http://pages.hmc.edu/harris/class/e85/ Harvey Mudd class on CPU architecture] that was referenced in [https://lug.mtu.edu/minutes/spring2022/meeting03.html the lecture]. [https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V-dp-0128200642/dp/0128200642/ The textbook] (ISBN 978-0128200643) is a fantastic resource and worthy of a genuine purchase (though, it is on a certain library online). [https://www.amazon.com/Digital-Design-Computer-Architecture-Harris-dp-0123944244/dp/0123944244/ His MIPS version] (ISBN 978-0123944245) is what MTU's computer organization class uses.

Hardware description languages (HDLs) are used to work with digital logic and generate CPUs. The main two languages used for HDL are [https://en.wikipedia.org/wiki/Verilog#Example Verilog] and [https://en.wikipedia.org/wiki/VHDL#Design_examples VHDL]. One must use VHDL or Verilog to work with digital logic and is a requirement to continue forward. MTU teaches via Verilog, though the industry standard seems to be closed to VHDL. Choose whichever you deem fit. If you use a language outside of VHDL or Verilog, you will not be marketable (props to you, since I loathe the term "marketable").

=== Projects ===
1. Follow [https://www.nand2tetris.org/ nand2tetris].

2. Design RISC-V CPU in Verilog. This is explained in [https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V-dp-0128200642/dp/0128200642/ ISBN 978-0128200643].

3. Design a 3-stage pipelined RISC-V CPU in Verilog (fetch, decode, execute). This is explained in [https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V-dp-0128200642/dp/0128200642/ ISBN 978-0128200643].

=== Tools ===

==== GTKWave ====

[http://gtkwave.sourceforge.net/ GTKWave] is a visualization tool for debugging your HDL.

==== IVerilog ====

[http://iverilog.icarus.com/ Icarus Verilog] is a tool used to "compile" your Verilog code to be used in GTKWave. In actuality, IVerilog generates a netlist whereby GTKWave can use this netlist to simulate your circuit.

== Layout of a chip ==

TODO: I'm not knowledgeable enough to know what steps to be done here.

== Advanced topics ==

=== Analog circuits ===

Analog circuits require fundamental knowledge of MOSFETs, JFETs and BJTs. TODO: Give links.

=== Reverse engineering ===

Reverse engineering chips is really fascinating and gives a good idea as to how engineers laid out the chips without requiring you to sign an NDA before looking at any of the designs.

A list:

* [http://www.righto.com/2015/10/inside-ubiquitous-741-op-amp-circuits.html Blog stepping through a reverse engineering a 741].

* [https://siliconpr0n.org/ IC] [https://siliconpr0n.org/wiki RE tutorial] and [https://siliconpr0n.org/map/ pictures] (Be warned, images are massive, typically 50 to 200 MB image).

* [https://zeptobars.com/en/ More IC pictures to practice on].

ASIC Design - Revision history

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